1. Technical Field
The present disclosure relates to a semiconductor device and to a method of fabricating the same and, more particularly, to a semiconductor device including a dual stress film and to a method of fabricating the same.
2. Description of the Related Art
Due to high integration and high speed of metal oxide semiconductor field effect transistors (MOSFET), various processes have been research to form transistors that do not generate errors and which have improved performance. Particularly, many processes are being developed to increase the mobility of electrons or holes to fabricate high-performance transistors.
A process of applying physical stress to a channel area to change an energy band structure of the channel area may be performed to increase the mobility of the electrons or the holes. For example, n-channel metal oxide semiconductors (NMOS) transistors have improved performance when tensile stress is applied to a channel, and p-channel metal oxide semiconductors (PMOS) transistors have improved performance when compressive stress is applied to a channel. Accordingly, a dual stress film structure where a tensile stress film is formed on the NMOS transistor and a compressive stress film is formed on the PMOS transistor to improve the performance of both the NMOS transistor and the PMOS transistor is being researched.
However, when a dual stress film is applied, an area where the tensile stress film and the compressive stress film partially overlap may be formed at the interface of the NMOS transistor and the PMOS transistor according to characteristics of devices or photolithography margins. The overlapping area of the stress film may be thicker than the area where the single stress film is layered. Therefore, when contact holes are formed through the single stress film and the overlapping area using an etching process, the contact holes may first be formed through the single stress film, and a lower structure of the contact holes which are formed beforehand may be attacked before the contact holes are formed through the overlapping area. Accordingly, the contact characteristics and the reliability of the semiconductor device may be reduced.